Joint evaluation of sparse models and silicon

Original brain-inspired CHT training meets Moffett’s sparse silicon, with joint results presented at CCF HPC 2026. From learning mechanisms to compute architecture, the collaboration connects the foundations of structural efficiency.

THE RESULT

7B model. 1:4 sparsity.
Up to 2.89× execution speedup.

Moffett’s disclosed same-platform compiler evaluation reports up to 2.89× execution speedup for a 7B model with 1:4 sparsity, compared with the dense baseline.

The joint result makes the value of structure learning measurable in silicon execution evaluation.

Read the published disclosure

7B MODEL · 1:4 SPARSITYSAME-PLATFORM COMPILER EVALUATION

2.89×

Peak execution speedup

Dense baseline1.00×

CHT + Moffett · 1:42.89×

Source: Moffett disclosure at CCF HPC 2026. Relative to the same-platform dense baseline. Compiler evaluation; deployment results depend on model, hardware and workload.

Co-design creates the advantage

CHT learns efficient connectivity; Moffett’s architecture executes highly sparse computation. Model, compiler and execution co-design translate learned structure into measurable compute gains.

SparseMind’s contribution

Contributes original CHT training methods and highly sparse model research, enabling models to learn efficient connectivity.

Moffett’s contribution

Contributes highly sparse chip architecture and compiler evaluation, mapping model structure to hardware execution advantages.

Co-innovation opens new markets

Model–chip co-design opens a path from execution efficiency to stronger service economics. End-to-end evaluation of quality, latency, throughput and cost connects performance gains to specific business value.

Data note: 2.89× is the same-platform compiler evaluation result for a 7B model with 1:4 sparsity. Source: a Moffett-authored CCF HPC 2026 report published October 21, 2026.